1. Field Of The Invention
The present invention relates to circuits for monitoring power supply voltage levels in the field of nonvolatile memory devices.
2. Description Of Related Art
Flash EPROMs are a growing class of nonvolatile storage integrated circuits. These flash EPROMs have the capability of electrically erasing, programming or reading a memory cell in the chip. The entire array can be simultaneously erased electrically. The flash EPROM can also be randomly read or written.
The cells themselves use only a single device per cell and are formed using so-called floating gate transistors in which the data is stored in a cell by charging or discharging the floating gate. The floating gate is a conductive material, typically made of polysilicon, which are insulated from the channel of the transistor by a thin layer of oxide or other insulating material, and insulated from the control gate wordline of the transistor by a second layer of insulating material.
The act of charging the floating gate is termed the "program" step for a flash EPROM. This is accomplished through a so-called hot electron injection by establishing a large positive voltage between the gate and source, as much as 12 volts, and a positive voltage between the drain and source, for instance, 6 volts.
The act of discharging the floating gate is called the "erase" function for a flash EPROM. This erasure function is typically carried out by a Fowler-Nordheim (F-N) tunneling mechanism between the floating gate and the source of the transistor (source erase) or between the floating gate and the substrate (channel erase). For instance, a source erase operation is induced by establishing a large positive voltage from the source to gate, while floating the drain of the respective memory cell. This positive voltage may be as much as 12 volts.
Given that flash EPROMs can be programmed or erased by applying voltage to the device, systems incorporating flash EPROMs often design capabilities to program and erase the flash EPROMs. In order for a system to provide capabilities to program and erase the flash EPROMs, the system has to provide not only a Vcc voltage but also a Vpp voltage. Vcc is generally a 5 volt supply for controlling the logic in the read mode of the nonvolatile memory device. Vpp is a 12 volt supply used in combination with Vcc for controlling the programming and erasing modes of the nonvolatile memory device.
A problem arises when the computer system which uses nonvolatile memory as part of its storage elements goes through a power up or power down sequence. A power up sequence refers to the moment a user starts the computer system, while a power down sequence refers to the moment a user turns off the computer system. During these power up and power down sequences, the system power supplies for Vcc and Vpp rise and fall through their proper operating ranges. When this occurs, control signals within the system are not guaranteed to be valid. These invalid signals can cause inadvertent programming or erasing of the nonvolatile data. In certain instances, permanent damage to the nonvolatile memory can occur.
Protection circuits have been designed to prevent the application of Vcc voltage or Vpp voltage to the nonvolatile device when the voltages are below the proper operating level. One such system is disclosed in Baker, et al., U.S. Pat. No. 4,975,883, issued Dec. 4, 1990. Baker, et al. uses two comparators to detect the proper voltage level. One for the Vcc voltage and one for the Vpp voltage. The comparators constantly dissipate a substantial amount of DC power. Further, many of the devices in the voltage detector of Baker, et al. are exposed to the high Vpp voltage. Devices subjected to the high voltage of Vpp require additional protection to reduce the stress on such components. Also, to reduce power dissipation, longer channel devices are needed which take significant space on the chip. Accordingly, disadvantages of Baker, et al. include comparators that dissipate DC power, requirement that circuits provide for high voltage protection, and the overall complexity of the detection circuit.
Therefore, it is desirable to design a voltage protection circuit that improves and overcomes the disadvantages of the prior art.